Microsoft presents Maia 200, the AI ​​accelerator chip that maximizes inference efficiency

Microsoft has announced the launch of Maia 200 an artificial intelligence (AI) accelerator chip designed specifically for modern reasoning and extensive language models.

Maia 200 is optimized specifically for AI inference, offering more efficient performance per dollar as a result of a new system and silicon architecture designed to maximize inference efficiency.

Provides 10.1 PFLOPS at 4-bit precision (FP4) and about 5 PFLOPS on 8 bits (FP8). According to Microsoft, it offers three times the FP4 performance of the third-generation Amazon Trainium and higher FP8 performance than Google’s seventh-generation TPU.

Additionally, it combines 272MB of inline SRAM with 216GB of HBM3e, providing 7TB/s of HBM bandwidth capacity to serve data-intensive operations, while minimizing off-chip traffic, which, as Microsoft explains, reduces HBM’s bandwidth demand and improves overall energy efficiency.

The technology company claims that, in practical terms, a Maia 200 node can run the largest models currently available on the market, with plenty of room for even larger models in the future.

Maia is there deployed in Microsoft’s US Central data center region. The first Maia 200 systems are already powering new models from the Microsoft Superintelligence team, accelerating Microsoft Foundry projects, and supporting Microsoft Copilot.