IBM announced the world’s first 0.7 nm chip

Theo Interesting EngineeringIBM’s technology to make chips smaller than 1 nanometer based on a new three-dimensional transistor architecture, helping to overcome current limits in chip miniaturization. The 0.7 nm chip contains nearly 100 billion transistors on a fingernail-sized die, nearly double the transistor density of the 2 nm chip announced by IBM in 2021.

Company representatives said the new technology can provide 50% higher performance or up to 70% power savings compared to 2 nm models, benefiting artificial intelligence systems, cloud infrastructure and consumer electronics in the future. Its solution comes as the semiconductor industry faces the growing challenge of shrinking transistor sizes using conventional designs. IBM claims the company’s design will pave the way to continue miniaturizing chips even as they approach atomic size.

The 0.7 nm chip uses an advanced design called “nanostack”. Unlike traditional chips that arrange transistors on a horizontal plane, nanostack applies a vertical stacking structure, thereby integrating more components in the same area. This design also allows the use of different materials in separate layers, helping engineers optimize performance and power consumption.

Jay Gambetta, IBM Research Director and IBM Fellow, shared: “The new breakthrough helps bring technology beyond the nanometer era to the atomic scale. With nanostack architecture, we not only create smaller transistors but also change chip manufacturing methods in a more powerful and energy-efficient way.”

IBM cooperates in developing semiconductor chip manufacturing technology with Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions. IBM experts conducted several tests at the company’s semiconductor research facility in Albany, New York and confirmed that the nanostack architecture can perform computational functions and put it into production.

This technology also helps shrink memory size. With the size of the SRAM cell (the surface of a basic memory cell on a semiconductor chip used to store 1 bit of data) reduced by 40%, chipmakers can build denser and more efficient processors while supporting increased memory demands from AI tasks, according to Ars Technica. IBM expects commercial application of chips using nanostack structure as early as within the next 5 years.

Nanometer (nm) technically refers to the width of the gate on a transistor. Smaller gates allow more transistors to be squeezed into the same area, making the processor more powerful. Chips initially used transistors with gate widths measured in centimeters, which were gradually reduced to millimeters and micrometers. By the late 1990s, advances in photolithography and materials science allowed the transition to nanometer-sized transistors (1 nm equals 0.000001 mm), equivalent to the diameter of human DNA. This advance significantly improves transistor density, processing speed and reduces power consumption. The most advanced chips being produced commercially reach 2 nm.